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» A Comparison of Two Architectural Power Models
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DATE
2010
IEEE
157views Hardware» more  DATE 2010»
15 years 2 months ago
RMOT: Recursion in model order for task execution time estimation in a software pipeline
Abstract—This paper addresses the problem of execution time estimation for tasks in a software pipeline independent of the application structure or the underlying architecture. A...
Nabeel Iqbal, M. A. Siddique, Jörg Henkel
ICCAD
2003
IEEE
325views Hardware» more  ICCAD 2003»
15 years 2 months ago
Hardware Scheduling for Dynamic Adaptability using External Profiling and Hardware Threading
While performance, area, and power constraints have been the driving force in designing current communication-enabled embedded systems, post-fabrication and run-time adaptability ...
Brian Swahn, Soha Hassoun
VLSID
2002
IEEE
160views VLSI» more  VLSID 2002»
15 years 10 months ago
PREDICTMOS MOSFET Model and its Application to Submicron CMOS Inverter Delay Analysis
Predictive delay analysis is presented for a representative CMOS inverter with submicron device size using PREDICTMOS MOSFET model. As against SPICE, which adopts a time consuming...
A. B. Bhattacharyya, Shrutin Ulman
UM
2010
Springer
15 years 2 months ago
PersonisJ: Mobile, Client-Side User Modelling
The increasing trend towards powerful mobile phones opens many possibilities for valuable personalised services to be available on the phone. Client-side personalisation for these ...
Simon Gerber, Michael Fry, Judy Kay, Bob Kummerfel...
AAAI
2010
14 years 7 months ago
Latent Class Models for Algorithm Portfolio Methods
Different solvers for computationally difficult problems such as satisfiability (SAT) perform best on different instances. Algorithm portfolios exploit this phenomenon by predicti...
Bryan Silverthorn, Risto Miikkulainen