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CJ
1999
87views more  CJ 1999»
15 years 3 months ago
Evolution-Based Scheduling of Computations and Communications on Distributed Memory Multicomputers
We present a compiler optimization approach that uses the simulated evolution (SE) paradigm to enhance the finish time of heuristically scheduled computations with communication t...
Mayez A. Al-Mouhamed
SASP
2008
IEEE
183views Hardware» more  SASP 2008»
15 years 10 months ago
Application Acceleration with the Explicitly Parallel Operations System - the EPOS Processor
Different approaches have been proposed over the years for automatically transforming High-Level-Languages (HLL) descriptions of applications into custom hardware implementations. ...
Alexandros Papakonstantinou, Deming Chen, Wen-mei ...
135
Voted
CODES
2004
IEEE
15 years 7 months ago
Operation tables for scheduling in the presence of incomplete bypassing
Register bypassing is a powerful and widely used feature in modern processors to eliminate certain data hazards. Although complete bypassing is ideal for performance, bypassing ha...
Aviral Shrivastava, Eugene Earlie, Nikil D. Dutt, ...
131
Voted
CGO
2003
IEEE
15 years 7 months ago
Optimal and Efficient Speculation-Based Partial Redundancy Elimination
Existing profile-guided partial redundancy elimination (PRE) methods use speculation to enable the removal of partial redundancies along more frequently executed paths at the expe...
Qiong Cai, Jingling Xue
140
Voted
IACR
2011
132views more  IACR 2011»
14 years 3 months ago
Tamper-Proof Circuits: How to Trade Leakage for Tamper-Resilience
Abstract. Tampering attacks are cryptanalytic attacks on the implementation of cryptographic algorithms (e.g., smart cards), where an adversary introduces faults with the hope that...
Sebastian Faust, Krzysztof Pietrzak, Daniele Ventu...