223 search results - page 17 / 45 » A Compiler Scheme for Reusing Intermediate Computation Resul... |
RTCSA
2006
IEEE
15 years 3 months ago
2006
IEEE
To support high-performance and low-power for multimedia applications and for hand-held devices, embedded VLIW DSP processors are of research focus. With the tight resource constr...
ARITH
2005
IEEE
14 years 11 months ago
2005
IEEE
This paper presents a novel error-free (infinite-precision) architecture for the fast implementation of both 2-D Discrete Cosine Transform and Inverse DCT. The architecture uses a...
83
Voted
DAC
2002
ACM
15 years 10 months ago
2002
ACM
In this paper, we present a compiler strategy to optimize data accesses in regular array-intensive applications running on embedded multiprocessor environments. Specifically, we p...
ICS
2009
Tsinghua U.
15 years 4 months ago
2009
Tsinghua U.
Tiling is a crucial loop transformation for generating high performance code on modern architectures. Efficient generation of multilevel tiled code is essential for maximizing da...
JRTIP
2008
14 years 9 months ago
2008
Abstract In an effort to achieve lower bandwidth requirements, video compression algorithms have become increasingly complex. Consequently, the deployment of these algorithms on Fi...