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IEEEPACT
2000
IEEE
15 years 2 months ago
Exploring Sub-Block Value Reuse for Superscalar Processors
The performance potential of a value reuse mechanism depends on its reuse detection time, the number of reuse opportunities, and the amount of work saved by skipping each reuse un...
Jian Huang, David J. Lilja
CAL
2005
14 years 9 months ago
On Reusing the Results of Pre-Executed Instructions in a Runahead Execution Processor
Previous research on runahead execution took it for granted as a prefetch-only technique. Even though the results of instructions independent of an L2 miss are correctly computed d...
Onur Mutlu, Hyesoon Kim, Jared Stark, Yale N. Patt
MEMOCODE
2010
IEEE
14 years 7 months ago
Compilation of imperative synchronous programs with refined clocks
To overcome over-synchronization in synchronous programs, we recently introduced clock refinement to our synchronous programming language Quartz. This extension basically allows p...
Mike Gemunde, Jens Brandt, Klaus Schneider
LCTRTS
2010
Springer
14 years 7 months ago
Compiler directed network-on-chip reliability enhancement for chip multiprocessors
Chip multiprocessors (CMPs) are expected to be the building blocks for future computer systems. While architecting these emerging CMPs is a challenging problem on its own, program...
Ozcan Ozturk, Mahmut T. Kandemir, Mary Jane Irwin,...
DATE
2003
IEEE
97views Hardware» more  DATE 2003»
15 years 2 months ago
Enhancing Speedup in Network Processing Applications by Exploiting Instruction Reuse with Flow Aggregation
Instruction reuse is a microarchitectural technique that improves the execution time of a program by removing redundant computations at run-time. Although this is the job of an op...
G. Surendra, Subhasis Banerjee, S. K. Nandy