As across-chip interconnect delays can exceed a clock cycle, wire pipelining becomes essential in high performance designs. Although it allows higher clock frequencies, it may cha...
This paper presents a technique for preprocessing combinational logic before technology mapping. The technique is based on the representation of combinational logic using And-Inve...
Alan Mishchenko, Satrajit Chatterjee, Robert K. Br...
Design and verification of systems at the Register-Transfer (RT) or behavioral level require the ability to reason at higher levels of abstraction. Difference logic consists of an...
Abstract— A common approach to designing feedback controllers for nonlinear partial differential equations (PDEs) is to linearize the system about an equilibrium and use the line...
In this paper four mechanisms, fine and coarse grained fitness rating, linguistic evaluation and active user intervention are compared for use in the multi-objective IGA. The inte...