The floating-point unit in the Synergistic Processor Element of the 1st generation multi-core CELL Processor is described. The FPU supports 4-way SIMD single precision and intege...
With continued reductions in feature size, additional functionality may be added to future microprocessors to boost the performance of important application domains. Due to growth...
Clusters of SMPs are becoming increasingly common. However, the shared memory design of SMPs and the consequential contention between system processors for access to main memory c...
FreeWill+ is a framework that aims at integrating various animation techniques for controlling human-like characters. With heterogeneity and multi-layering as its main design prin...
Query processing on mobile sensor networks requires efficient indexing and partitioning of the data space to support efficient routing as the network scales up. Building an index ...