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ARITH
2005
IEEE
15 years 10 months ago
The Vector Floating-Point Unit in a Synergistic Processor Element of a CELL Processor
The floating-point unit in the Synergistic Processor Element of the 1st generation multi-core CELL Processor is described. The FPU supports 4-way SIMD single precision and intege...
Silvia M. Müller, Christian Jacobi 0002, Hwa-...
145
Voted
ASAP
2005
IEEE
142views Hardware» more  ASAP 2005»
15 years 10 months ago
Decimal Floating-Point Square Root Using Newton-Raphson Iteration
With continued reductions in feature size, additional functionality may be added to future microprocessors to boost the performance of important application domains. Due to growth...
Liang-Kai Wang, Michael J. Schulte
PDP
2005
IEEE
15 years 10 months ago
Memory Bandwidth Aware Scheduling for SMP Cluster Nodes
Clusters of SMPs are becoming increasingly common. However, the shared memory design of SMPs and the consequential contention between system processors for access to main memory c...
Evangelos Koukis, Nectarios Koziris
ACMACE
2005
ACM
15 years 10 months ago
Integrate and conquer: the next generation of intelligent avatars
FreeWill+ is a framework that aims at integrating various animation techniques for controlling human-like characters. With heterogeneity and multi-layering as its main design prin...
Jaroslaw Francik, Adam Szarowicz
152
Voted
MOBIDE
2005
ACM
15 years 10 months ago
Tolerance of localization imprecision in efficiently managing mobile sensor databases
Query processing on mobile sensor networks requires efficient indexing and partitioning of the data space to support efficient routing as the network scales up. Building an index ...
Lin Xiao, Aris M. Ouksel