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DAC
2003
ACM
16 years 5 months ago
Test cost reduction for SOCs using virtual TAMs and lagrange multipliers
Recent advances in tester technology have led to automatic test equipment (ATE) that can operate at up to several hundred MHz. However, system-on-chip (SOC) scan chains typically ...
Anuja Sehgal, Vikram Iyengar, Mark D. Krasniewski,...
DAC
2003
ACM
16 years 5 months ago
Dynamic hardware/software partitioning: a first approach
Partitioning an application among software running on a microprocessor and hardware co-processors in on-chip configurable logic has been shown to improve performance and energy co...
Greg Stitt, Roman L. Lysecky, Frank Vahid
DAC
2003
ACM
16 years 5 months ago
Power grid reduction based on algebraic multigrid principles
With the scaling of technology, power grid noise is becoming increasingly significant for circuit performance. A typical power grid circuit contains millions of linear elements, m...
Haihua Su, Emrah Acar, Sani R. Nassif
DAC
2004
ACM
16 years 5 months ago
Placement feedback: a concept and method for better min-cut placements
The advent of strong multi-level partitioners has made topdown min-cut placers a favored choice for modern placer implementations. We examine terminal propagation, an important st...
Andrew B. Kahng, Sherief Reda
DAC
2004
ACM
16 years 5 months ago
Profile-based optimal intra-task voltage scheduling for hard real-time applications
This paper presents a set of comprehensive techniques for the intratask voltage scheduling problem to reduce energy consumption in hard real-time tasks of embedded systems. Based ...
Jaewon Seo, Taewhan Kim, Ki-Seok Chung