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JRTIP
2008
249views more  JRTIP 2008»
15 years 3 months ago
Model-based mapping of reconfigurable image registration on FPGA platforms
Abstract Image registration is a computationally intensive application in the medical imaging domain that places stringent requirements on performance and memory management efficie...
Mainak Sen, Yashwanth Hemaraj, William Plishker, R...
MP
2006
88views more  MP 2006»
15 years 3 months ago
Two-edge connected subgraphs with bounded rings: Polyhedral results and Branch-and-Cut
Abstract. We consider the network design problem which consists in determining at minimum cost a 2-edge connected network such that the shortest cycle (a "ring") to which...
Bernard Fortz, Ali Ridha Mahjoub, S. Thomas McCorm...
IJNSEC
2007
137views more  IJNSEC 2007»
15 years 3 months ago
An FPGA-based AES-CCM Crypto Core For IEEE 802.11i Architecture
The widespread adoption of IEEE 802.11 wireless networks has brought its security paradigm under active research. One of the important research areas in this field is the realiza...
Arshad Aziz, Nassar Ikram
TCAD
2008
114views more  TCAD 2008»
15 years 3 months ago
Word-Level Predicate-Abstraction and Refinement Techniques for Verifying RTL Verilog
el Predicate Abstraction and Refinement Techniques for Verifying RTL Verilog Himanshu Jain, Daniel Kroening, Natasha Sharygina, and Edmund M. Clarke, Fellow, IEEE As a first step, ...
Himanshu Jain, Daniel Kroening, Natasha Sharygina,...
FPL
2010
Springer
129views Hardware» more  FPL 2010»
15 years 1 months ago
FPGA Implementations of the Round Two SHA-3 Candidates
Abstract--The second round of the NIST-run public competition is underway to find a new hash algorithm(s) for inclusion in the NIST Secure Hash Standard (SHA-3). This paper present...
Brian Baldwin, Andrew Byrne, Liang Lu, Mark Hamilt...