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DAC
2005
ACM
14 years 11 months ago
VLIW: a case study of parallelism verification
Parallelism in processor architecture and design imposes a verification challenge as the exponential growth in the number of execution combinations becomes unwieldy. In this paper...
Allon Adir, Yaron Arbetman, Bella Dubrov, Yossi Li...
LCTRTS
2007
Springer
15 years 3 months ago
Interface synthesis for heterogeneous multi-core systems from transaction level models
This paper presents a tool for automatic synthesis of RTL interfaces for heterogeneous MPSoC from transaction level models (TLMs). The tool captures the communication parameters i...
Hansu Cho, Samar Abdi, Daniel Gajski
ATVA
2008
Springer
144views Hardware» more  ATVA 2008»
14 years 11 months ago
Tests, Proofs and Refinements
1 : Logic in Specification and Verification (abstract) Natarajan Shankar (SRI) Session Chair : Sungdeok Cha 12 : 00 13 : 00 Lunch 13 : 00 15 : 00 2 : Boolean Modeling of Cell Biolo...
Sriram K. Rajamani
DAC
2009
ACM
15 years 10 months ago
A real-time program trace compressor utilizing double move-to-front method
This paper introduces a new unobtrusive and cost-effective method for the capture and compression of program execution traces in real-time, which is based on a double move-to-fron...
Vladimir Uzelac, Aleksandar Milenkovic
116
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SIGIR
2012
ACM
13 years 3 days ago
An uncertainty-aware query selection model for evaluation of IR systems
We propose a mathematical framework for query selection as a mechanism for reducing the cost of constructing information retrieval test collections. In particular, our mathematica...
Mehdi Hosseini, Ingemar J. Cox, Natasa Milic-Frayl...