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DELTA
2004
IEEE
15 years 8 months ago
Scan Test of IP Cores in an ATE Environment
Manufacturing test of chips made of multiple IP cores requires different techniques if ATE is used. As scan chains are commonly used as access paths to the DUT, ATE architectures ...
Luca Schiano, Yong-Bin Kim, Fabrizio Lombardi
168
Voted
ASWEC
2009
IEEE
15 years 2 months ago
From Requirements to Embedded Software - Formalising the Key Steps
Failure of a design to satisfy a system's requirements can result in schedule and cost overruns. When using current approaches, ensuring requirements are satisfied is often d...
Toby Myers, R. Geoff Dromey
CODES
2009
IEEE
15 years 11 months ago
FlexRay schedule optimization of the static segment
The FlexRay bus is the prospective automotive standard communication system. For the sake of a high flexibility, the protocol includes a static time-triggered and a dynamic event...
Martin Lukasiewycz, Michael Glaß, Jürge...
160
Voted
ECRTS
2009
IEEE
15 years 2 months ago
Partitioned Fixed-Priority Preemptive Scheduling for Multi-core Processors
Abstract--Energy and thermal considerations are increasingly driving system designers to adopt multi-core processors. In this paper, we consider the problem of scheduling periodic ...
Karthik Lakshmanan, Ragunathan Rajkumar, John P. L...
160
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LCPC
2004
Springer
15 years 10 months ago
Power-Aware Scheduling for Parallel Security Processors with Analytical Models
Techniques to reduce power dissipation for embedded systems have recently come into sharp focus in the technology development. Among these techniques, dynamic voltage scaling (DVS)...
Yung-Chia Lin, Yi-Ping You, Chung-Wen Huang, Jenq ...