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MICRO
2008
IEEE
114views Hardware» more  MICRO 2008»
15 years 6 months ago
Toward a multicore architecture for real-time ray-tracing
Significant improvement to visual quality for real-time 3D graphics requires modeling of complex illumination effects like soft-shadows, reflections, and diffuse lighting intera...
Venkatraman Govindaraju, Peter Djeu, Karthikeyan S...
ISCA
2010
IEEE
176views Hardware» more  ISCA 2010»
15 years 3 months ago
Forwardflow: a scalable core for power-constrained CMPs
Chip Multiprocessors (CMPs) are now commodity hardware, but commoditization of parallel software remains elusive. In the near term, the current trend of increased coreper-socket c...
Dan Gibson, David A. Wood
CSB
2004
IEEE
108views Bioinformatics» more  CSB 2004»
15 years 3 months ago
Embedded Computation of Maximum-Likelihood Phylogeny Inference Using Platform FPGA
Our previous work to accelerate phylogeny inference using HW/SW(Hardware/Software) co-design has recently been extended to a more powerful embedded computing platform. In this pla...
Terrence S. T. Mak, Kai-Pui Lam
DAC
2002
ACM
16 years 16 days ago
Exploiting operation level parallelism through dynamically reconfigurable datapaths
Increasing non-recurring engineering (NRE) and mask costs are making it harder to turn to hardwired Application Specific Integrated Circuit (ASIC) solutions for high performance a...
Zhining Huang, Sharad Malik
IEEEPACT
2006
IEEE
15 years 5 months ago
Adaptive reorder buffers for SMT processors
In SMT processors, the complex interplay between private and shared datapath resources needs to be considered in order to realize the full performance potential. In this paper, we...
Joseph J. Sharkey, Deniz Balkan, Dmitry Ponomarev