Parasitic extraction techniques are used to estimate signal delay in VLSI chips. Inductance extraction is a critical component of the parasitic extraction process in which on-chip ...
In this paper, we describe our experience in writing parallel numerical algorithms using Hierarchically Tiled Arrays (HTAs). HTAs are classes of objects that encapsulate parallelis...
Ganesh Bikshandi, Basilio B. Fraguela, Jia Guo, Ma...
Volumetric effects such as beams of light through participating media are an important component in the appearance of the natural world. Many such effects can be faithfully modele...
Ilya Baran, Jiawen Chen, Jonathan Ragan-Kelley, Fr...
Current high-end parallel systems achieve low-latency, highbandwidth network communication through the use of aggressive design techniques and expensive mechanical and electrical ...
We build on work in designing modeling languages for hybrid systems in the development of CTA, the Cottbus Timed Automata. Our design features a facility to specify a hybrid system...