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» A Counterflow Pipeline Experiment
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ICCAD
2006
IEEE
169views Hardware» more  ICCAD 2006»
15 years 10 months ago
Microarchitecture parameter selection to optimize system performance under process variation
Abstract— Design variability due to within-die and die-todie process variations has the potential to significantly reduce the maximum operating frequency and the effective yield...
Xiaoyao Liang, David Brooks
ACCV
2009
Springer
15 years 8 months ago
Multi-view Texturing of Imprecise Mesh
Abstract. Reprojection of texture issued from cameras on a mesh estimated from multi-view reconstruction is often the last stage of the pipeline, used for rendering, visualization,...
Ehsan Aganj, Pascal Monasse, Renaud Keriven
ASPLOS
2004
ACM
15 years 7 months ago
Scalable selective re-execution for EDGE architectures
Pipeline flushes are becoming increasingly expensive in modern microprocessors with large instruction windows and deep pipelines. Selective re-execution is a technique that can r...
Rajagopalan Desikan, Simha Sethumadhavan, Doug Bur...
97
Voted
IPPS
1996
IEEE
15 years 6 months ago
A Hierarchical Parallel Processing System for the Multipass-Rendering Method
The multipass-rendering method integrating radiosity with ray-tracing gives one of the best solutions for synthesizing photo-realistic images. However, the method is also computat...
Hiroaki Kobayashi, Hitoshi Yamauchi, Yuichiro Toh,...
CODES
2006
IEEE
15 years 5 months ago
Application specific forwarding network and instruction encoding for multi-pipe ASIPs
Small area and code size are two critical design issues in most of embedded system designs. In this paper, we tackle these issues by customizing forwarding networks and instructio...
Swarnalatha Radhakrishnan, Hui Guo, Sri Parameswar...