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» A Counterflow Pipeline Experiment
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RTSS
2008
IEEE
15 years 8 months ago
WCET Analysis of Multi-level Non-inclusive Set-Associative Instruction Caches
With the advent of increasingly complex hardware in realtime embedded systems (processors with performance enhancing features such as pipelines, cache hierarchy, multiple cores), ...
Damien Hardy, Isabelle Puaut
117
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VR
2008
IEEE
173views Virtual Reality» more  VR 2008»
15 years 8 months ago
Rapid Creation of Large-scale Photorealistic Virtual Environments
The rapid and efficient creation of virtual environments has become a crucial part of virtual reality applications. In particular, civil and defense applications often require an...
Charalambos Poullis, Suya You, Ulrich Neumann
109
Voted
DATE
2007
IEEE
128views Hardware» more  DATE 2007»
15 years 8 months ago
Accounting for cache-related preemption delay in dynamic priority schedulability analysis
Recently there has been considerable interest in incorporating timing effects of microarchitectural features of processors (e.g. caches and pipelines) into the schedulability anal...
Lei Ju, Samarjit Chakraborty, Abhik Roychoudhury
ESCIENCE
2007
IEEE
15 years 8 months ago
eResearch Solutions for High Throughput Structural Biology
Structural biology research places significant demands upon computing and informatics infrastructure. Protein production, crystallization and X-ray data collection require solutio...
Noel G. Faux, Anthony Beitz, Mark A. Bate, Abdulla...
CHES
2007
Springer
136views Cryptology» more  CHES 2007»
15 years 8 months ago
CAIRN 2: An FPGA Implementation of the Sieving Step in the Number Field Sieve Method
The hardness of the integer factorization problem assures the security of some public-key cryptosystems including RSA, and the number field sieve method (NFS), the most efficient ...
Tetsuya Izu, Jun Kogure, Takeshi Shimoyama