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» A Counterflow Pipeline Experiment
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DAC
2005
ACM
16 years 20 days ago
Microarchitecture-aware floorplanning using a statistical design of experiments approach
Since across-chip interconnect delays can exceed a clock cycle in nanometer technologies, it has become essential in high performance designs to add flip-flops on wires with multi...
Vidyasagar Nookala, Ying Chen, David J. Lilja, Sac...
ANLP
2000
81views more  ANLP 2000»
15 years 1 months ago
Experimenting with the Interaction between Aggregation and Text Structuring
In natural language generation, different generation tasks often interact with each other in a complex way, which is hard to capture in the pipeline architecture described by Reit...
Hua Cheng
ASYNC
2002
IEEE
90views Hardware» more  ASYNC 2002»
15 years 4 months ago
An Event Spacing Experiment
Events in self-timed rings can propagate evenly spaced or as bursts. By studying these phenomena, we obtain a better understanding of the underlying dynamics of self-timed pipelin...
Mark R. Greenstreet, Anthony Winstanley, Aurelien ...
CF
2004
ACM
15 years 5 months ago
Fault tolerant clockless wave pipeline design
This paper presents a fault tolerant design technique for the clockless wave pipeline. The specific architectural model investigated in this paper is the two-phase clockless asyn...
T. Feng, Byoungjae Jin, J. Wang, Nohpill Park, Yon...