233 search results - page 4 / 47 » A Counterflow Pipeline Experiment |
CC
2000
Springer
14 years 11 months ago
2000
Springer
The performance of a Java Virtual Machine (JVM) interpreter running on a very long instruction word (VLIW) processor can be improved by means of pipelining. While one bytecode is i...
121
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ISCA
2011
IEEE
14 years 3 months ago
2011
IEEE
A growing body of work has compiled a strong case for the single-ISA heterogeneous multi-core paradigm. A single-ISA heterogeneous multi-core provides multiple, differently-design...
114
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DELTA
2010
IEEE
15 years 4 months ago
2010
IEEE
— FPGAs, (Field-Programmable Gate Arrays) are often used for embedded image processing applications. Parallelism, and in particular pipelining, is the most suitable architecture ...
ASPDAC
2006
ACM
15 years 5 months ago
2006
ACM
— A new algorithm is proposed to reduce the number of intermediate registers of a pipelined circuit using a combination of multi-clock cycle paths and clock scheduling. The algor...
FPL
2006
Springer
15 years 3 months ago
2006
Springer
We present a heavily parametrized tool suite that allows the modeling and exploration of heterogeneous, coarse-grained, heavily pipelined reconfigurable architectures. Our tools p...