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» A Decompression Architecture for Low Power Embedded Systems
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138
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ISLPED
2010
ACM
128views Hardware» more  ISLPED 2010»
14 years 10 months ago
Rank-aware cache replacement and write buffering to improve DRAM energy efficiency
DRAM power and energy efficiency considerations are becoming increasingly important for low-power and mobile systems. Using lower power modes provided by commodity DRAM chips redu...
Ahmed M. Amin, Zeshan Chishti
117
Voted
RTSS
2007
IEEE
15 years 6 months ago
An Energy-Driven Design Methodology for Distributing DSP Applications across Wireless Sensor Networks
Wireless sensor network (WSN) applications have been studied extensively in recent years. Such applications involve resource-limited embedded sensor nodes that have small size and...
Chung-Ching Shen, William Plishker, Shuvra S. Bhat...
117
Voted
RTAS
2010
IEEE
14 years 10 months ago
Timing Analysis for TDMA Arbitration in Resource Sharing Systems
Abstract--Modern computing systems have adopted multicore architectures and multiprocessor systems on chip (MPSoCs) for accommodating the increasing demand on computation power. Ho...
Andreas Schranzhofer, Jian-Jia Chen, Lothar Thiele
137
Voted
NOCS
2009
IEEE
15 years 7 months ago
Best of both worlds: A bus enhanced NoC (BENoC)
While NoCs are efficient in delivering high throughput point-to-point traffic, their multi-hop operation is too slow for latency sensitive signals. In addition, NoCS are inefficie...
Ran Manevich, Isask'har Walter, Israel Cidon, Avin...
121
Voted
CODES
2010
IEEE
14 years 10 months ago
A greedy buffer allocation algorithm for power-aware communication in body sensor networks
Monitoring human movements using wireless sensory devices promises to revolutionize the delivery of healthcare services. In spite of their potentials for many application domains,...
Hassan Ghasemzadeh, Roozbeh Jafari