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» A Decompression Architecture for Low Power Embedded Systems
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ISQED
2006
IEEE
107views Hardware» more  ISQED 2006»
15 years 6 months ago
On Optimizing Scan Testing Power and Routing Cost in Scan Chain Design
— With advanced VLSI manufacturing technology in deep submicron (DSM) regime, we can integrate entire electronic systems on a single chip (SoC). Due to the complexity in SoC desi...
Li-Chung Hsu, Hung-Ming Chen
119
Voted
MONET
2011
14 years 7 months ago
iDSRT: Integrated Dynamic Soft Real-time Architecture for Critical Infrastructure Data Delivery over WLAN
Critical Infrastructures (CIs) such as the Power Grid play an important role in our lives. Of all important aspects of CIs, real-time data delivery is the most important one becaus...
Hoang Viet Nguyen, Raoul Rivas, Klara Nahrstedt
70
Voted
GLVLSI
2003
IEEE
166views VLSI» more  GLVLSI 2003»
15 years 5 months ago
Exponential split accumulator for high-speed reduced area low-power direct digital frequency synthesizers
A new split accumulator architecture to be used in direct digital frequency synthesizers (DDFS) systems is presented. This new design eliminates the need of adders on the section ...
Edward Merlo, Kwang-Hyun Baek, Myung-Jun Choe
177
Voted
DAC
2006
ACM
16 years 1 months ago
Extending the lifetime of fuel cell based hybrid systems
Fuel cells are clean power sources that have much higher energy densities and lifetimes compared to batteries. However, fuel cells have limited load following capabilities and can...
Jianli Zhuo, Chaitali Chakrabarti, Naehyuck Chang,...
ISLPED
2005
ACM
111views Hardware» more  ISLPED 2005»
15 years 6 months ago
Energy reduction in multiprocessor systems using transactional memory
The emphasis in microprocessor design has shifted from high performance, to a combination of high performance and low power. Until recently, this trend was mostly true for uniproc...
Tali Moreshet, R. Iris Bahar, Maurice Herlihy