714 search results - page 11 / 143 » A Decompression Architecture for Low Power Embedded Systems |
110
click to vote
DCC
2000
IEEE
15 years 4 months ago
2000
IEEE
We present a novel algorithm that assigns codes to instructions during instruction code compression in order to minimize bus-related bit-toggling and thus reducing power consumpti...
155
Voted
SOSP
2001
ACM
15 years 9 months ago
2001
ACM
In recent years, there has been a rapid and wide spread of nontraditional computing platforms, especially mobile and portable computing devices. As applications become increasingl...
103
click to vote
ICCD
2006
IEEE
15 years 9 months ago
2006
IEEE
— Traditional level-one instruction caches and data caches for embedded systems typically have the same capacities. Configurable caches either shut down a part of the cache to su...
DATE
2007
IEEE
15 years 6 months ago
2007
IEEE
113
Voted
IJPP
2007
15 years 10 days ago
2007
