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» A Decompression Architecture for Low Power Embedded Systems
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94
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ISCAS
2006
IEEE
102views Hardware» more  ISCAS 2006»
15 years 6 months ago
A low power merge cell processor for real-time spike sorting in implantable neural prostheses
Extremely low power consumption is the critical constraint for designing implantable neural decoders that inter- Desired face directly with the nervous system. Typically a system w...
M. D. Linderman, T. H. Meng
85
Voted
IJCSA
2008
117views more  IJCSA 2008»
15 years 15 days ago
Altivec Vector Unit Customization for Embedded Systems
Vector extensions for general purpose processors are an efficient feature to address the growing performance demand of multimedia and computer vision applications. Embedded proces...
Tarik Saidani, Joel Falcou, Lionel Lacassagne, Sam...
80
Voted
DAC
2009
ACM
16 years 1 months ago
Low power gated bus synthesis using shortest-path Steiner graph for system-on-chip communications
Power consumption of system-level on-chip communications is becoming more significant in the overall system-on-chip (SoC) power as technology scales down. In this paper, we propos...
Renshen Wang, Nan-Chi Chou, Bill Salefski, Chung-K...
99
Voted
MAM
2002
110views more  MAM 2002»
15 years 5 days ago
Architecture of a fieldbus message scheduler coprocessor based on the planning paradigm
The use of a centralised planning scheduler in fieldbus-based systems requiring real-time operation has proved to be a good compromise between operational flexibility and timeline...
Ernesto Martins, Paulo A. C. S. Neves, José...
82
Voted
DATE
2010
IEEE
155views Hardware» more  DATE 2010»
15 years 5 months ago
Bitstream processing for embedded systems using C++ metaprogramming
—This paper suggests a new approach for bitstream processing of embedded systems, using a combination of C++ metaprogramming combined with architecture extensions of an customiza...
Reimund Klemm, Gerhard Fettweis