714 search results - page 38 / 143 » A Decompression Architecture for Low Power Embedded Systems |
92
Voted
VLSID
2006
IEEE
16 years 27 days ago
2006
IEEE
This article describes a standard cell based novel implementation of a low-power Viterbi Decoder (VD) targeted for the IEEE 802.11a Wireless LAN system. Multiple clock rates have ...
78
Voted
VLSID
2004
IEEE
16 years 27 days ago
2004
IEEE
This work presents a novel dynamic bias control technique to verify the circuit performance of the lowpower rail-to-rail input/output buffer amplifier, which can be operating in s...
93
Voted
DATE
2003
IEEE
15 years 5 months ago
2003
IEEE
Software implementations of channel decoding algorithms are attractive for communication systems with their large variety of existing and emerging standards due to their flexibil...
86
Voted
DAC
2001
ACM
16 years 1 months ago
2001
ACM
Due to larger buses (length, width) and deep sub-micron effects where coupling capacitances between bus lines are in the same order of magnitude as base capacitances, power consum...
78
Voted
VLSID
2007
IEEE
16 years 27 days ago
2007
IEEE
This paper proposes a data encoder to reduce switched capacitance on system bus. Our method focuses on transferring raw video data (pixels) between off-chip memory and on-chip mem...