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» A Decompression Architecture for Low Power Embedded Systems
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100
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DAC
2006
ACM
16 years 1 months ago
Multiprocessor system-on-chip data reuse analysis for exploring customized memory hierarchies
The increasing use of Multiprocessor Systems-on-Chip (MPSoCs) for high performance demands of embedded applications results in high power dissipation. The memory subsystem is a la...
Ilya Issenin, Erik Brockmeyer, Bart Durinck, Nikil...
80
Voted
DAC
2004
ACM
16 years 1 months ago
Design optimizations for microprocessors at low temperature
We investigate trade-offs in microprocessor frequency and system power achievable for low temperature operation in scaled high leakage technologies by combining refrigeration with...
Arman Vassighi, Ali Keshavarzi, Siva Narendra, Ger...
DAC
2011
ACM
14 years 10 days ago
EFFEX: an embedded processor for computer vision based feature extraction
The deployment of computer vision algorithms in mobile applications is growing at a rapid pace. A primary component of the computer vision software pipeline is feature extraction,...
Jason Clemons, Andrew Jones, Robert Perricone, Sil...
79
Voted
DAC
1997
ACM
15 years 4 months ago
Dynamic Communication Models in Embedded System Co-Simulation
Many co-simulation techniques either suffer from poor performance when simulating communications intensive systems, or they represent communications with a uniformly low level of ...
Ken Hines, Gaetano Borriello
DATE
2003
IEEE
130views Hardware» more  DATE 2003»
15 years 5 months ago
A Technique for High Ratio LZW Compression
Reduction of both the test suite size and the download time of test vectors is important in today's System-On-a-Chip designs. In this paper, a method for compressing the scan...
Michael J. Knieser, Francis G. Wolff, Christos A. ...