714 search results - page 49 / 143 » A Decompression Architecture for Low Power Embedded Systems |
146
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DAC
2004
ACM
16 years 7 months ago
2004
ACM
Code compression has been shown to be an effective technique to reduce code size in memory constrained embedded systems. It has also been used as a way to increase cache hit ratio...
145
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ICIP
1999
IEEE
16 years 7 months ago
1999
IEEE
A new chip-set for video display processing in a consumer television or set-top box is presented. Key aspect of the chip-set is a high flexibility and programmability of multi-win...
184
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JTRES
2010
ACM
15 years 6 months ago
2010
ACM
Chip-multiprocessors offer increased processing power at a low cost. However, in order to use them for real-time systems, tasks have to be scheduled efficiently and predictably. I...
154
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ASYNC
2000
IEEE
15 years 10 months ago
2000
IEEE
Self-timed systems often have to communicate with their environment through a clocked interface. For example, off-chip memory may require clocking and this can reduce the benefit...
166
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ISLPED
2003
ACM
15 years 11 months ago
2003
ACM
This paper addresses two aspects of low-power design for FPGA circuits. First, we present an RT-level power estimator for FPGAs with consideration of wire length. The power estima...