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» A Decompression Architecture for Low Power Embedded Systems
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96
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CAL
2002
15 years 11 days ago
Exploiting Fixed Programs in Embedded Systems: A Loop Cache Example
Embedded systems commonly execute one program for their lifetime. Designing embedded system architectures with configurable components, such that those components can be tuned to t...
Ann Gordon-Ross, Susan Cotterell, Frank Vahid
97
Voted
GLVLSI
2010
IEEE
164views VLSI» more  GLVLSI 2010»
15 years 5 months ago
Performance and energy trade-offs analysis of L2 on-chip cache architectures for embedded MPSoCs
On-chip memory organization is one of the most important aspects that can influence the overall system behavior in multiprocessor systems. Following the trend set by high-perform...
Mohamed M. Sabry, Martino Ruggiero, Pablo Garcia D...
WMPI
2004
ACM
15 years 6 months ago
Selective main memory compression by identifying program phase changes
During a program’s runtime, the stack and data segments of the main memory often contain much redundancy, which makes them good candidates for compression. Compression and decomp...
Doron Nakar, Shlomo Weiss
104
Voted
PACS
2000
Springer
83views Hardware» more  PACS 2000»
15 years 4 months ago
A Comparison of Two Architectural Power Models
Reducing power, on both a per cycle basis and as the total energy used over the lifetime of an application, has become more important as small and embedded devices become increasi...
Soraya Ghiasi, Dirk Grunwald
ASAP
2003
IEEE
107views Hardware» more  ASAP 2003»
15 years 5 months ago
Energy Aware Register File Implementation through Instruction Predecode
The register file is a power-hungry device in modern architectures. Current research on compiler technology and computer architectures encourages the implementation of larger dev...
José L. Ayala, Marisa Luisa López-Va...