714 search results - page 55 / 143 » A Decompression Architecture for Low Power Embedded Systems |
FTDCS
2004
IEEE
15 years 4 months ago
2004
IEEE
In this paper, we present a system architecture that allows users to interact with embedded systems located in their proximity using Smart Phones. We have identified four models o...
91
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IJES
2007
15 years 14 days ago
2007
: The power density in high performance systems continues to rise with every process technology generation, thereby increasing the operating temperature and creating ‘hot spotsâ€...
102
Voted
ASAP
2007
IEEE
15 years 7 months ago
2007
IEEE
Entropy encoding and decoding is a crucial part of any multimedia system that can be highly demanding in terms of computing power. Hardware implementation of typical compression a...
104
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CASES
2008
ACM
15 years 2 months ago
2008
ACM
This paper proposes a combination of circuit and architectural techniques to maximize leakage power reduction in embedded processor on-chip caches. It targets cache peripheral cir...
102
Voted
AHS
2006
IEEE
15 years 6 months ago
2006
IEEE
This paper describes the architecture of our dynamically reconfigurable Network-on-Chip (NoC) architecture that has been proposed for reconfigurable Multiprocessor system-on-chip ...