714 search results - page 66 / 143 » A Decompression Architecture for Low Power Embedded Systems |
92
Voted
ISLPED
2005
ACM
15 years 6 months ago
2005
ACM
Tuning a configurable cache subsystem to an application can greatly reduce memory hierarchy energy consumption. Previous tuning methods use a level one configurable cache only, or...
102
Voted
WSNA
2003
ACM
15 years 5 months ago
2003
ACM
Recent research in sensor networks has raised security issues for small embedded devices. Security concerns are motivated by the deployment of a large number of sensory devices in...
109
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AHS
2007
IEEE
15 years 4 months ago
2007
IEEE
In the system-on-chip (SoC) era, the growing number of functionalities included on a single chip requires the development of new design methodologies to keep the design complexity...
121
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CODES
2005
IEEE
15 years 6 months ago
2005
IEEE
Majority of existing works on system level power estimation have focused on the processor, while there are very few that address power consumption of peripherals in a SoC. With th...
114
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CAMP
2005
IEEE
15 years 2 months ago
2005
IEEE
Abstract— In this paper we address the problem of the architectural exploration from the energy/performance point of view of a VLIW processor for embedded systems. We also consid...