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» A Decompression Architecture for Low Power Embedded Systems
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ICCD
2002
IEEE
141views Hardware» more  ICCD 2002»
15 years 9 months ago
Embedded Operating System Energy Analysis and Macro-Modeling
A large and increasing number of modern embedded systems are subject to tight power/energy constraints. It has been demonstrated that the operating system (OS) can have a signifi...
Tat Kee Tan, Anand Raghunathan, Niraj K. Jha
82
Voted
IPPS
1995
IEEE
15 years 4 months ago
The RACE network architecture
The RACE R parallel computer system provides a highperformance parallel interconnection network at low cost. This paper describes the architecture and implementation of the RACE ...
Bradley C. Kuszmaul
103
Voted
ERSA
2008
145views Hardware» more  ERSA 2008»
15 years 2 months ago
Multicore Devices: A New Generation of Reconfigurable Architectures
For two decades, reconfigurable computing systems have provided an attractive alternative to fixed hardware solutions. Reconfigurable computing systems have demonstrated the low c...
Steven A. Guccione
74
Voted
ITC
1999
IEEE
78views Hardware» more  ITC 1999»
15 years 4 months ago
Minimized power consumption for scan-based BIST
Power consumption of digital systems may increase significantly during testing. In this paper, systems equipped with a scan-based built-in self-test like the STUMPS architecture a...
Stefan Gerstendörfer, Hans-Joachim Wunderlich
BSN
2009
IEEE
141views Sensor Networks» more  BSN 2009»
15 years 7 months ago
Low-Complexity, High-Throughput Multiple-Access Wireless Protocol for Body Sensor Networks
Wireless systems that form a body-area network must be made small and low power without sacrificing performance. To achieve high-throughput communication in low-cost wireless bod...
Seung-mok Yoo, Chong-Jing Chen, Pai H. Chou