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» A Decompression Architecture for Low Power Embedded Systems
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84
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ICCAD
2001
IEEE
86views Hardware» more  ICCAD 2001»
15 years 9 months ago
System-Level Exploration for Pareto-Optimal Configurations in Parameterized Systems-on-a-Chip
In this work, we provide a technique for efficiently exploring the configuration space of a parameterized system-on-a-chip (SOC) architecture to find all Pareto-optimal configurat...
Tony Givargis, Frank Vahid, Jörg Henkel
108
Voted
MOBISYS
2007
ACM
16 years 6 days ago
Triage: balancing energy and quality of service in a microserver
The ease of deployment of battery-powered and mobile systems is pushing the network edge far from powered infrastructures. A primary challenge in building untethered systems is of...
Nilanjan Banerjee, Jacob Sorber, Mark D. Corner, S...
PATMOS
2007
Springer
15 years 6 months ago
XEEMU: An Improved XScale Power Simulator
Energy efficiency is a top requirement in embedded system design. Understanding the complex issue of software power consumption in early design phases is of extreme importance to m...
Zoltán Herczeg, Ákos Kiss, Daniel Sc...
115
Voted
TCAD
2002
158views more  TCAD 2002»
15 years 7 days ago
Static power modeling of 32-bit microprocessors
The paper presents a novel strategy aimed at modelling instruction energy consumption of 32-bits microprocessors. Differently from former approaches, the proposed instruction-level...
Carlo Brandolese, Fabio Salice, William Fornaciari...
127
Voted
DSD
2008
IEEE
187views Hardware» more  DSD 2008»
15 years 7 months ago
How to Live with Uncertainties: Exploiting the Performance Benefits of Self-Timed Logic In Synchronous Design
Ultra low power digital systems are key for any future wireless sensor nodes but also inside nomadic embedded systems (such as inside the digital front end of software defined rad...
Giacomo Paci, A. Nackaerts, Francky Catthoor, Luca...