714 search results - page 82 / 143 » A Decompression Architecture for Low Power Embedded Systems |
82
Voted
ISLPED
2000
ACM
15 years 5 months ago
2000
ACM
Memory-processor integration o ers new opportunities for reducing the energy of a system. In the case of embedded systems, one solution consists of mapping the most frequently acc...
132
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PPL
2008
15 years 16 days ago
2008
As the number of integrated IP cores in the current System-on-Chips (SoCs) keeps increasing, communication requirements among cores can not be sufficiently satisfied using either ...
113
Voted
GLVLSI
2005
IEEE
15 years 6 months ago
2005
IEEE
The instruction cache is a popular target for optimizations of microprocessor-based systems because of the cache’s high impact on system performance and power, and because of th...
120
Voted
SEUS
2008
IEEE
15 years 7 months ago
2008
IEEE
Abstract— This paper presents SW synthesis using Embedded System Environment (ESE), a tool set for design of multicore embedded systems. We propose a classification of multicore...
CF
2006
ACM
15 years 6 months ago
2006
ACM
In this paper, we investigate the power implications of tile size selection for tile-based processors. We refer to this investigation as a tile granularity study. This is accompli...