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» A Decompression Architecture for Low Power Embedded Systems
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CODES
2003
IEEE
15 years 5 months ago
Security wrappers and power analysis for SoC technologies
Future wireless internet enabled devices will be increasingly powerful supporting many more applications including one of the most crucial, security. Although SoCs offer more resi...
Catherine H. Gebotys, Y. Zhang
EH
2004
IEEE
117views Hardware» more  EH 2004»
15 years 4 months ago
Multi-objective Optimization of a Parameterized VLIW Architecture
The use of Application Specific Instruction-set Processors (ASIP) in embedded systems is a solution to the problem of increasing complexity in the functions these systems have to ...
Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi,...
125
Voted
IPSN
2010
Springer
14 years 9 months ago
i-MAC - a MAC that learns
Traffic patterns in manufacturing machines exhibit strong temporal correlations due to the underlying repetitive nature of their operations. A MAC protocol can potentially learn t...
Krishna Kant Chintalapudi
97
Voted
RTCSA
2005
IEEE
15 years 6 months ago
An Overview of the VigilNet Architecture
Battlefield surveillance often involves a high element of risk for military operators. Hence, it is very important for the military to execute unmanned surveillance by using larg...
Tian He, Liqian Luo, Ting Yan, Lin Gu, Qing Cao, G...
111
Voted
VLSID
2001
IEEE
164views VLSI» more  VLSID 2001»
16 years 28 days ago
An Efficient Parallel Transparent Bist Method For Multiple Embedded Memory Buffers
In this paper, we propose a new transparent built-in self-test ( TBIST ) method to test multiple embedded memory arrays with various sizes in parallel. First, a new transparent tes...
Der-Cheng Huang, Wen-Ben Jone, Sunil R. Das