59 search results - page 2 / 12 » A Delay Model and Speculative Architecture for Pipelined Rou... |
SC
2009
ACM
15 years 5 months ago
2009
ACM
The present contribution explores the design space for virtual channel (VC) and switch allocators in network-on-chip (NoC) routers. Based on detailed RTL-level implementations, we...
ASPDAC
2009
ACM
15 years 2 months ago
2009
ACM
Abstract-- The increasing wire delay constraints in deep submicron VLSI designs have led to the emergence of scalable and modular Network-on-Chip (NoC) architectures. As the power ...
80
Voted
FPL
2006
Springer
15 years 1 months ago
2006
Springer
We present a heavily parametrized tool suite that allows the modeling and exploration of heterogeneous, coarse-grained, heavily pipelined reconfigurable architectures. Our tools p...
94
Voted
NOCS
2010
IEEE
14 years 8 months ago
2010
IEEE
Router microarchitecture plays a central role in the performance of an on-chip network (NoC). Buffers are needed in routers to house incoming flits which cannot be immediately forw...
106
Voted
FPL
2006
Springer
15 years 1 months ago
2006
Springer
Interconnect delays are becoming an increasingly significant part of the critical path delay for circuits implemented in FPGAs. Pipelined interconnects have been proposed to addre...