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ICCAD
2001
IEEE
128views Hardware» more  ICCAD 2001»
15 years 10 months ago
An Assembly-Level Execution-Time Model for Pipelined Architectures
The aim of this work is to provide an elegant and accurate static execution timing model for 32-bit microprocessor instruction sets, covering also inter–instruction effects. Suc...
Giovanni Beltrame, Carlo Brandolese, William Forna...
139
Voted
MASCOTS
2004
15 years 2 months ago
An Optimisation Model for a Two-Node Router Network
Architectural designs for routers and networks of routers to support mobile communication are analysed for their end-to-end performance using a simple Markov model. In view of the...
Nalan Gülpinar, Peter G. Harrison, Berç...
ICC
2008
IEEE
151views Communications» more  ICC 2008»
15 years 7 months ago
Hop-by-Hop Local Flow Control over InterPlaNetary Networks Based on DTN Architecture
—Deep space communications are an important research line in scientific community. The possibility of performing the communication between earth and other planets is an excitant ...
Floriano De Rango, Mauro Tropea, Giovanni Battista...
ISCA
2008
IEEE
201views Hardware» more  ISCA 2008»
15 years 1 months ago
iDEAL: Inter-router Dual-Function Energy and Area-Efficient Links for Network-on-Chip (NoC) Architectures
Network-on-Chip (NoC) architectures have been adopted by a growing number of multi-core designs as a flexible and scalable solution to the increasing wire delay constraints in the...
Avinash Karanth Kodi, Ashwini Sarathy, Ahmed Louri
ICPP
1991
IEEE
15 years 4 months ago
Two Techniques to Enhance the Performance of Memory Consistency Models
The memory consistency model supported by a multiprocessor directly affects its performance. Thus, several attempts have been made to relax the consistency models to allow for mor...
Kourosh Gharachorloo, Anoop Gupta, John L. Henness...