59 search results - page 5 / 12 » A Delay Model and Speculative Architecture for Pipelined Rou... |
DAC
2006
ACM
16 years 2 months ago
2006
ACM
Packet editing is a fundamental building block of data communication systems such as switches and routers. Circuits that implement this function are critical and define the featur...
GLOBECOM
2006
IEEE
15 years 7 months ago
2006
IEEE
— Emulating Output Queued (OQ) Switch with sustainable implementation cost and low fixed delay is always preferable in designing high performance routers. The SwitchMemory-Switch...
116
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INFOCOM
2002
IEEE
15 years 6 months ago
2002
IEEE
A multigigabit IP router may receive several millions packets per second from each input link. For each packet, the router needs to find the longest matching prefix in the forw...
103
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MICRO
2009
IEEE
15 years 7 months ago
2009
IEEE
Performance and power are the first order design metrics for Network-on-Chips (NoCs) that have become the de-facto standard in providing scalable communication backbones for mult...
SIGCOMM
2009
ACM
15 years 7 months ago
2009
ACM
New protocols for the data link and network layer are being proposed to address limitations of current protocols in terms of scalability, security, and manageability. High-speed r...