59 search results - page 6 / 12 » A Delay Model and Speculative Architecture for Pipelined Rou... |
125
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INFOCOM
2010
IEEE
14 years 11 months ago
2010
IEEE
—The inherent support in routers (SNMP counters or NetFlow) is not sufficient to diagnose performance problems in IP networks, especially for flow-specific problems where the ...
114
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ICCD
2005
IEEE
15 years 6 months ago
2005
IEEE
Nanoelectronic devices are expected to have extremely high and variable fault rates; thus future processor architectures based on these unreliable devices need to be built with fa...
114
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ISPASS
2009
IEEE
15 years 8 months ago
2009
IEEE
Until very recently, microprocessor designs were computation-centric. On-chip communication was frequently ignored. This was because of fast, single-cycle on-chip communication. T...
ISCA
1998
IEEE
15 years 5 months ago
1998
IEEE
Control-flow misprediction penalties are a major impediment to high performance in wide-issue superscalar processors. In this paper we present Selective Eager Execution (SEE), an ...
111
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HPCA
2008
IEEE
16 years 1 months ago
2008
IEEE
Simultaneous Multithreading (SMT) attempts to keep a dynamically scheduled processor's resources busy with work from multiple independent threads. Threads with longlatency st...