An approach to robust system level mixed signal design is presented based on analog platforms. The bottom-up characterization phase of platform components provides accurate perfor...
Fernando De Bernardinis, Pierluigi Nuzzo, Alberto ...
System Level Design (SLD) is widely seen as a solution for bridging the gap between chip complexity and design productivity of Systems on Chip (SoC). SLD relieves the designer fro...
In this paper, we propose an effective automatic generation approach for a Cycle-Count Accurate Memory Model (CCAMM) from the Clocked Finite State Machine (CFSM) of the Cycle Accu...
— It is predicted that 70% of the chip area will be occupied by memories in future system-onchips. The minimization of on-chip memory hence becomes increasingly important for cos...
In the design of highly complex, heterogeneous, and concurrent systems, deadlock detection and resolution remains an important issue. In this paper, we systematically analyze the ...
Xi Chen, Abhijit Davare, Harry Hsieh, Alberto L. S...