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MEMOCODE
2003
IEEE
15 years 5 months ago
LOTOS Code Generation for Model Checking of STBus Based SoC: the STBus interconnect
In the design process of SoC (System on Chip), validation is one of the most critical and costly activity. The main problem for industrial companies like STMicroelectronics, stand...
Pierre Wodey, Geoffrey Camarroque, Fabrice Baray, ...
100
Voted
RTAS
2008
IEEE
15 years 6 months ago
WCET Analysis for Multi-Core Processors with Shared L2 Instruction Caches
Multi-core chips have been increasingly adopted by microprocessor industry. For real-time systems to safely harness the potential of multi-core computing, designers must be able t...
Jun Yan, Wei Zhang
83
Voted
MODELS
2007
Springer
15 years 6 months ago
Statechart Development Beyond WYSIWYG
Modeling systems based on semi-formal graphical formalisms, such as Statecharts, have become standard practice in the design of reactive embedded devices. Statecharts are often mor...
Steffen Prochnow, Reinhard von Hanxleden
105
Voted
CSE
2009
IEEE
15 years 3 months ago
Rotation Scheduling and Voltage Assignment to Minimize Energy for SoC
— Low energy consumption is a critical issue in embedded systems design. As the technology feature sizes of SoC (Systems on Chip) become smaller and smaller, the percentage of le...
Meikang Qiu, Laurence Tianruo Yang, Edwin Hsing-Me...
CASES
2008
ACM
15 years 2 months ago
Multi-granularity sampling for simulating concurrent heterogeneous applications
Detailed or cycle-accurate/bit-accurate (CABA) simulation is a critical phase in the design flow of embedded systems. However, with increasing system complexity, full detailed sim...
Melhem Tawk, Khaled Z. Ibrahim, Smaïl Niar