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104
Voted
ISLPED
2007
ACM
123views Hardware» more  ISLPED 2007»
15 years 2 months ago
Approximation algorithms for power minimization of earliest deadline first and rate monotonic schedules
We address power minimization of earliest deadline first and ratemonotonic schedules by voltage and frequency scaling. We prove that the problems are NP-hard, and present (1+ ) f...
Sushu Zhang, Karam S. Chatha, Goran Konjevod
DATE
2008
IEEE
145views Hardware» more  DATE 2008»
15 years 7 months ago
Minimizing Virtual Channel Buffer for Routers in On-chip Communication Architectures
We present a novel methodology for design space exploration using a two-steps scheme to optimize the number of virtual channel buffers (buffers take the premier share of the route...
Mohammad Abdullah Al Faruque, Jörg Henkel
115
Voted
VALUETOOLS
2006
ACM
167views Hardware» more  VALUETOOLS 2006»
15 years 6 months ago
Detailed cache simulation for detecting bottleneck, miss reason and optimization potentialities
Cache locality optimization is an efficient way for reducing the idle time of modern processors in waiting for needed data. This kind of optimization can be achieved either on the...
Jie Tao, Wolfgang Karl
105
Voted
EMSOFT
2009
Springer
15 years 7 months ago
Clock-driven distributed real-time implementation of endochronous synchronous programs
An important step in model-based embedded system design consists in mapping functional specifications and their tasks/operations onto execution architectures and their ressources...
Dumitru Potop-Butucaru, Robert de Simone, Yves Sor...
CODES
2005
IEEE
15 years 6 months ago
Memory access optimizations in instruction-set simulators
Design of programmable processors and embedded applications requires instruction-set simulators for early exploration and validation of candidate architectures. Interpretive simul...
Mehrdad Reshadi, Prabhat Mishra