894 search results - page 94 / 179 » A Dependability-Driven System-Level Design Approach for Embe... |
120
Voted
MTDT
2003
IEEE
15 years 8 months ago
2003
IEEE
Memory cores (especially SRAM cores) used on a system chip usually come from a memory compiler. Commercial memory compilers have their limitation— a large memory may need to be ...
125
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DAC
2005
ACM
16 years 4 months ago
2005
ACM
We propose two novel integration techniques -- bypass and bookkeeping -- in the memory controller to address the cache coherence compatibility issue of a non-shared bus heterogene...
113
Voted
ICCAD
2008
IEEE
16 years 12 days ago
2008
IEEE
—The microprocessor verification challenge becomes higher in the on-chip bus (OCB) than in the unit-level. Especially for the external interrupts, since they interface with othe...
131
Voted
CASES
2009
ACM
15 years 10 months ago
2009
ACM
A common problem in event-triggered real-time systems is caused by low-priority tasks that are implemented as interrupt handlers interrupting and disturbing high-priority tasks th...
149
Voted
TECS
2008
15 years 3 months ago
2008
tion. Transaction Level Modeling (TLM) has been proposed to abstract communication for highspeed system simulation and rapid design space exploration. Although being widely accepte...