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SBACPAD
2008
IEEE
170views Hardware» more  SBACPAD 2008»
15 years 9 months ago
Using Analytical Models to Efficiently Explore Hardware Transactional Memory and Multi-Core Co-Design
Transactional memory is emerging as a parallel programming paradigm for multi-core processors. Despite the recent interest in transactional memory, there has been no study to char...
James Poe, Chang-Burm Cho, Tao Li
ICCAD
1995
IEEE
129views Hardware» more  ICCAD 1995»
15 years 6 months ago
Activity-driven clock design for low power circuits
In this paper we investigate activity-driven clock trees to reduce the dynamic power consumption of synchronous digital CMOS circuits. Sections of an activity-driven clock tree ca...
Gustavo E. Téllez, Amir H. Farrahi, Majid S...
CPHYSICS
2006
119views more  CPHYSICS 2006»
15 years 3 months ago
GDF: A tool for function estimation through grammatical evolution
This article introduces a tool for data fitting that is based on genetic programming and especially on the grammatical evolution technique. The user needs to input a series of poi...
Ioannis G. Tsoulos, Dimitris Gavrilis, Evangelos D...
IMR
2005
Springer
15 years 8 months ago
Design and Implementation of a Corporate Mesh Object
Today, finite element technologies allow engineers to analyze complex assemblies and subsystems. With CPU power constantly increasing, it is not unreasonable to state that the eng...
John Svitek, Wa Kwok, Joseph R. Tristano
DAC
2003
ACM
15 years 8 months ago
Low-power design methodology for an on-chip bus with adaptive bandwidth capability
This paper describes a low-power design methodology for a bus architecture based on hybrid current/voltage mode signaling for deep sub-micrometer on-chip interconnects that achiev...
Rizwan Bashirullah, Wentai Liu, Ralph K. Cavin III