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DATE
2006
IEEE
104views Hardware» more  DATE 2006»
15 years 3 months ago
Integrated placement and skew optimization for rotary clocking
—The clock distribution network is a key component of any synchronous VLSI design. High power dissipation and pressure volume temperature-induced variations in clock skew have st...
Ganesh Venkataraman, Jiang Hu, Frank Liu, Cliff C....
MEMOCODE
2005
IEEE
15 years 3 months ago
Extended abstract: a race-free hardware modeling language
We describe race-free properties of a hardware description language called GEZEL. The language describes networks of cycle-true finite-state-machines with datapaths (FSMDs). We de...
Patrick Schaumont, Sandeep K. Shukla, Ingrid Verba...
GECCO
2005
Springer
140views Optimization» more  GECCO 2005»
15 years 3 months ago
CGP visits the Santa Fe trail: effects of heuristics on GP
GP uses trees to represent chromosomes. The user defines the representation space by defining the set of functions and terminals to label the nodes in the trees, and GP searches t...
Cezary Z. Janikow, Christopher J. Mann
MICRO
2003
IEEE
166views Hardware» more  MICRO 2003»
15 years 3 months ago
Razor: A Low-Power Pipeline Based on Circuit-Level Timing Speculation
With increasing clock frequencies and silicon integration, power aware computing has become a critical concern in the design of embedded processors and systems-on-chip. One of the...
Dan Ernst, Nam Sung Kim, Shidhartha Das, Sanjay Pa...
DSN
2002
IEEE
15 years 2 months ago
Ditto Processor
Concentration of design effort for current single-chip Commercial-Off-The-Shelf (COTS) microprocessors has been directed towards performance. Reliability has not been the primary ...
Shih-Chang Lai, Shih-Lien Lu, Jih-Kwon Peir