126 search results - page 24 / 26 » A Design Methodology for the Exploitation of High Level Comm... |
HPCA
2005
IEEE
13 years 12 months ago
2005
IEEE
Future high-performance billion-transistor processors are likely to employ partitioned architectures to achieve high clock speeds, high parallelism, low design complexity, and low...
COMSWARE
2007
IEEE
14 years 19 days ago
2007
IEEE
—Sensor networks represent a new frontier in technology that holds the promise of unprecedented levels of autonomy in the execution of complex dynamic missions by harnessing the ...
DAC
2008
ACM
14 years 7 months ago
2008
ACM
In this paper, a novel automatic approach for the concurrent topology and routing optimization that achieves a high quality network layout is proposed. This optimization is based ...
SIGCOMM
2009
ACM
14 years 24 days ago
2009
ACM
The routing architecture of the original 4.4BSD [3] kernel has been deployed successfully without major design modification for over 15 years. In the unified routing architectur...
DAC
2005
ACM
14 years 7 months ago
2005
ACM
Power has become a critical concern for battery-driven computing systems, on which many applications that are run are interactive. System-level voltage scaling techniques, such as...