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HPCA
1995
IEEE
13 years 9 months ago
Program Balance and Its Impact on High Performance RISC Architectures
Information on the behavior of programs is essential for deciding the number and nature of functional units in high performance architectures. In this paper, we present studies on...
Lizy Kurian John, Vinod Reddy, Paul T. Hulina, Lee...
HPCA
2004
IEEE
14 years 6 months ago
Exploring Wakeup-Free Instruction Scheduling
Design of wakeup-free issue queues is becoming desirable due to the increasing complexity associated with broadcast-based instruction wakeup. The effectiveness of most wakeup-free...
Jie S. Hu, Narayanan Vijaykrishnan, Mary Jane Irwi...
AAAI
2010
13 years 4 months ago
Latent Class Models for Algorithm Portfolio Methods
Different solvers for computationally difficult problems such as satisfiability (SAT) perform best on different instances. Algorithm portfolios exploit this phenomenon by predicti...
Bryan Silverthorn, Risto Miikkulainen
IEEEPACT
2006
IEEE
14 years 9 days ago
Branch predictor guided instruction decoding
Fast instruction decoding is a challenge for the design of CISC microprocessors. A well-known solution to overcome this problem is using a trace cache. It stores and fetches alrea...
Oliverio J. Santana, Ayose Falcón, Alex Ram...
HPCA
1999
IEEE
13 years 10 months ago
Instruction Recycling on a Multiple-Path Processor
Processors that can simultaneously execute multiple paths of execution will only exacerbate the fetch bandwidth problem already plaguing conventional processors. On a multiple-pat...
Steven Wallace, Dean M. Tullsen, Brad Calder