162 search results - page 17 / 33 » A Distributed Cache Coherence Protocol for Hypercube Multipr... |
90
Voted
IPPS
2006
IEEE
15 years 3 months ago
2006
IEEE
Step caches are caches in which data entered to an cache array is kept valid only until the end of ongoing step of execution. Together with an advanced pipelined multithreaded arc...
ASPLOS
2008
ACM
14 years 11 months ago
2008
ACM
Integrating more processor cores on-die has become the unanimous trend in the microprocessor industry. Most of the current research thrusts using chip multiprocessors (CMPs) as th...
107
Voted
HPCA
2012
IEEE
13 years 5 months ago
2012
IEEE
Large-scale CMPs with hundreds of cores require a directory-based protocol to maintain cache coherence. However, previously proposed coherence directories are hard to scale beyond...
101
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MAM
2002
14 years 9 months ago
2002
Bus-based shared memory multiprocessors with private caches and snooping write-invalidate cache coherence protocols are dominant form of small- to medium-scale parallel machines t...
PPOPP
1997
ACM
15 years 1 months ago
1997
ACM
Some of the most common parallel programming idioms include locks, barriers, and reduction operations. The interaction of these programming idioms with the multiprocessor's c...