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WMPI
2004
ACM
15 years 5 months ago
Memory coherence activity prediction in commercial workloads
Abstract. Recent research indicates that prediction-based coherence optimizations offer substantial performance improvements for scientific applications in distributed shared memor...
Stephen Somogyi, Thomas F. Wenisch, Nikolaos Harda...
IEEEPACT
2009
IEEE
15 years 6 months ago
DDCache: Decoupled and Delegable Cache Data and Metadata
Abstract—In order to harness the full compute power of manycore processors, future designs must focus on effective utilization of on-chip cache and bandwidth resources. In this p...
Hemayet Hossain, Sandhya Dwarkadas, Michael C. Hua...
94
Voted
SSS
2010
Springer
128views Control Systems» more  SSS 2010»
14 years 10 months ago
On Transactional Scheduling in Distributed Transactional Memory Systems
We present a distributed transactional memory (TM) scheduler called Bi-interval that optimizes the execution order of transactional operations to minimize conflicts. Bi-interval c...
Junwhan Kim, Binoy Ravindran
103
Voted
ASAP
2005
IEEE
182views Hardware» more  ASAP 2005»
15 years 5 months ago
A Thread and Data-Parallel MPEG-4 Video Encoder for a System-On-Chip Multiprocessor
We studied the dynamic instruction count reduction for a single-thread, vectorized and a multi-threaded, non-vectorized, MPEG-4 video encoder. Results indicate a maximum improveme...
Tom R. Jacobs, José L. Núñez-...
VLSID
2002
IEEE
152views VLSI» more  VLSID 2002»
16 years 1 days ago
Verification of an Industrial CC-NUMA Server
Directed test program-based verification or formal verification methods are usually quite ineffective on large cachecoherent, non-uniform memory access (CC-NUMA) multiprocessors b...
Rajarshi Mukherjee, Yozo Nakayama, Toshiya Mima