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» A Distributed Control Path Architecture for VLIW Processors
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HOTI
2005
IEEE
15 years 9 months ago
Hybrid Cache Architecture for High Speed Packet Processing
: The exposed memory hierarchies employed in many network processors (NPs) are expensive in terms of meeting the worst-case processing requirement. Moreover, it is difficult to ef...
Zhen Liu, Kai Zheng, Bin Liu
ISCA
2002
IEEE
115views Hardware» more  ISCA 2002»
15 years 8 months ago
ReVive: Cost-Effective Architectural Support for Rollback Recovery in Shared-Memory Multiprocessors
This paper presents ReVive, a novel general-purpose rollback recovery mechanism for shared-memory multiprocessors. ReVive carefully balances the conflicting requirements of avail...
Milos Prvulovic, Josep Torrellas, Zheng Zhang
IPPS
2000
IEEE
15 years 8 months ago
Fault-Tolerant Distributed-Shared-Memory on a Broadcast-Based Interconnection Network
The Simultaneous Optical Multiprocessor Exchange Bus (SOME-Bus) is a low-latency, high-bandwidth interconnection network which directly links arbitrary pairs of processor nodes wit...
Diana Hecht, Constantine Katsinis
136
Voted
ICC
2007
IEEE
198views Communications» more  ICC 2007»
15 years 10 months ago
On Control Plane for Service Provisioning in Light-trail WDM Optical Ring Networks
: A light-trail is a generalized lightpath that enables multiple nodes to statistically share an optical communication path (wavelength bus). A light-trail is different from a ligh...
Ashwin Gumaste, Janak Chandarana, Paresh Bafna, Na...
ISSAC
2007
Springer
132views Mathematics» more  ISSAC 2007»
15 years 10 months ago
Adaptive loops with kaapi on multicore and grid: applications in symmetric cryptography
The parallelization of two applications in symmetric cryptography is considered: block ciphering and a new method based on random sampling for the selection of basic substitution ...
Vincent Danjean, Roland Gillard, Serge Guelton, Je...