Sciweavers

238 search results - page 3 / 48
» A Distributed Control Path Architecture for VLIW Processors
Sort
View
115
Voted
LCTRTS
2007
Springer
15 years 7 months ago
Tetris: a new register pressure control technique for VLIW processors
The run-time performance of VLIW (very long instruction word) microprocessors depends heavily on the effectiveness of its associated optimizing compiler. Typical VLIW compiler pha...
Weifeng Xu, Russell Tessier
109
Voted
ISSS
1998
IEEE
124views Hardware» more  ISSS 1998»
15 years 5 months ago
Data-Path Synthesis of VLIW Video Signal Processors
This paper describes a methodology for synthesizing the data-path of a Very Long Instruction Word (VLIW) based Video Signal Processor (VSP). Offering both performance and programm...
Zhao Wu, Wayne Wolf
123
Voted
LCTRTS
2007
Springer
15 years 7 months ago
Enabling compiler flow for embedded VLIW DSP processors with distributed register files
High-performance and low-power VLIW DSP processors are increasingly deployed on embedded devices to process video and multimedia applications. For reducing power and cost in desig...
Chung-Kai Chen, Ling-Hua Tseng, Shih-Chang Chen, Y...
77
Voted
RSP
2007
IEEE
110views Control Systems» more  RSP 2007»
15 years 7 months ago
Pre- and Post-Fabrication Architecture Exploration for Partially Reconfigurable VLIW Processors
Anupam Chattopadhyay, Z. Rakosi, Kingshuk Karuri, ...
113
Voted
RSP
2005
IEEE
155views Control Systems» more  RSP 2005»
15 years 6 months ago
Optimization Techniques for ADL-Driven RTL Processor Synthesis
Nowadays, Architecture Description Languages (ADLs) are getting popular to speed up the development of complex SoC design, by performing the design space explon a higher level of ...
Oliver Schliebusch, Anupam Chattopadhyay, Ernst Ma...