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» A Distributed Control Path Architecture for VLIW Processors
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CONPAR
1992
15 years 1 months ago
Asynchronous Polycyclic Architecture
The Asynchronous Polycyclic Architecture (APA) is a new processor design for numerically intensive applications. APA resembles the VLIW architecture, in that it provides independen...
Geraldo Lino de Campos
VLSISP
2008
159views more  VLSISP 2008»
14 years 9 months ago
Effective Code Generation for Distributed and Ping-Pong Register Files: A Case Study on PAC VLIW DSP Cores
The compiler is generally regarded as the most important software component that supports a processor design to achieve success. This paper describes our application of the open re...
Yung-Chia Lin, Chia-Han Lu, Chung-Ju Wu, Chung-Lin...
73
Voted
MICRO
2003
IEEE
147views Hardware» more  MICRO 2003»
15 years 2 months ago
Flexible Compiler-Managed L0 Buffers for Clustered VLIW Processors
Wire delays are a major concern for current and forthcoming processors. One approach to attack this problem is to divide the processor into semi-independent units referred to as c...
Enric Gibert, F. Jesús Sánchez, Anto...
IPPS
2003
IEEE
15 years 2 months ago
Using Incorrect Speculation to Prefetch Data in a Concurrent Multithreaded Processor
Concurrent multithreaded architectures exploit both instruction-level and thread-level parallelism through a combination of branch prediction and thread-level control speculation. ...
Ying Chen, Resit Sendag, David J. Lilja
IEEEPACT
2002
IEEE
15 years 2 months ago
Optimizing Loop Performance for Clustered VLIW Architectures
Modern embedded systems often require high degrees of instruction-level parallelism (ILP) within strict constraints on power consumption and chip cost. Unfortunately, a high-perfo...
Yi Qian, Steve Carr, Philip H. Sweany