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HPCA
2009
IEEE
15 years 10 months ago
Adaptive Spill-Receive for robust high-performance caching in CMPs
In a Chip Multi-Processor (CMP) with private caches, the last level cache is statically partitioned between all the cores. This prevents such CMPs from sharing cache capacity in r...
Moinuddin K. Qureshi
HPCA
2009
IEEE
15 years 10 months ago
Hardware-software integrated approaches to defend against software cache-based side channel attacks
Software cache-based side channel attacks present serious threats to modern computer systems. Using caches as a side channel, these attacks are able to derive secret keys used in ...
Jingfei Kong, Onur Aciiçmez, Jean-Pierre Se...
WMPI
2004
ACM
15 years 3 months ago
The Opie compiler from row-major source to Morton-ordered matrices
The Opie Project aims to develop a compiler to transform C codes written for row-major matrix representation into equivalent codes for Morton-order matrix representation, and to a...
Steven T. Gabriel, David S. Wise
CCR
2010
184views more  CCR 2010»
14 years 10 months ago
Characterising temporal distance and reachability in mobile and online social networks
The analysis of social and technological networks has attracted a lot of attention as social networking applications and mobile sensing devices have given us a wealth of real data...
John Tang, Mirco Musolesi, Cecilia Mascolo, Vito L...
HPCA
2009
IEEE
15 years 10 months ago
Dacota: Post-silicon validation of the memory subsystem in multi-core designs
The number of functional errors escaping design verification and being released into final silicon is growing, due to the increasing complexity and shrinking production schedules ...
Andrew DeOrio, Ilya Wagner, Valeria Bertacco