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» A Dynamic Multithreading Processor
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IPPS
2006
IEEE
15 years 8 months ago
Reducing the associativity and size of step caches in CRCW operation
Step caches are caches in which data entered to an cache array is kept valid only until the end of ongoing step of execution. Together with an advanced pipelined multithreaded arc...
M. Forsell
HIPC
2005
Springer
15 years 8 months ago
Preemption Adaptivity in Time-Published Queue-Based Spin Locks
Abstract. The proliferation of multiprocessor servers and multithreaded applications has increased the demand for high-performance synchronization. Traditional scheduler-based lock...
Bijun He, William N. Scherer III, Michael L. Scott
PDCAT
2004
Springer
15 years 7 months ago
An In-Order SMT Architecture with Static Resource Partitioning for Consumer Applications
Abstract. This paper proposes a simplified simultaneous multithreading (SMT) architecture aiming at CPU cores of embedded SoCs for consumer applications. This architecture reduces...
Byung In Moon, Hongil Yoon, Ilgun Yun, Sungho Kang
GI
2003
Springer
15 years 7 months ago
Evaluation of Thread-Based Virtual Duplex Systems in Embedded Environments
: Virtual duplex systems have emerged as an alternative to traditional duplex systems, trading structural for temporal redundancy. When used in dependable embedded systems, virtual...
Jörg Keller, Andreas Grävinghoff
HPCS
2002
IEEE
15 years 7 months ago
An Evaluation of Thread Migration for Exploiting Distributed Array Locality
Thread migration is one approach to remote memory accesses on distributed memory parallel computers. In thread migration, threads of control migrate between processors to access d...
Stephen Jenks, Jean-Luc Gaudiot