1834 search results - page 141 / 367 » A Dynamic Multithreading Processor |
131
Voted
CF
2005
ACM
15 years 4 months ago
2005
ACM
In modern superscalar processors, the complex instruction scheduler could form the critical path of the pipeline stages and limit the clock cycle time. In addition, complex schedu...
129
Voted
DSD
2010
IEEE
15 years 2 months ago
2010
IEEE
—Periodic on-chip scan-based tests have to be applied to a many-core processor SoC to improve its dependability. An infrastructural IP module has been designed and incorporated i...
126
Voted
LCTRTS
2007
Springer
15 years 8 months ago
2007
Springer
The run-time performance of VLIW (very long instruction word) microprocessors depends heavily on the effectiveness of its associated optimizing compiler. Typical VLIW compiler pha...
121
click to vote
ARVLSI
1997
IEEE
15 years 6 months ago
1997
IEEE
This paper describes the architecture and implementation of a high-speed decompression engine for embedded processors. The engine is targeted to processors where embedded programs...
125
Voted
CF
2010
ACM
15 years 7 months ago
2010
ACM
We develop two simple interval-based models for dynamic superscalar processors. These models allow us to: i) predict with great accuracy performance and power consumption under va...